Print control logic circuitry for on-the-fly printers

ABSTRACT

Print control logic circuitry for use in high speed &#39;&#39;&#39;&#39;on-thefly&#39;&#39;&#39;&#39; impact printers, wherein at least one, but preferably a plurality of independent, but interconnected data processing circuit modules, each including a separate free-running memory with logic controlled dual line storage areas, effects sequential character printing in a given line as the print data is being received, and simultaneous therewith allows for the temporary storage of print data for the next adjacent line, when required. Through the utilization of modular construction, each circuit module may advantageously be of identical design, and formed on a single integrated circuit chip, preferably using inexpensive MOSFET&#39;&#39;S exhibiting relatively slow switching speeds, with no sacrifice in printer performance.

United States Patent Brodrueck Nov. 5, 1974 Primary Examiner-Robert E.Pulfrey Assistant Examiner-Edward M. Coven [75] Inventor: Rletlef A.Brodrueck, Northbrook, Attorney, Agem r Firm K R. Bergum; J. L Lundis[73] Assignee: Teletype Corporation, Skokie, Ill. [57] ABSTRACT [22]Filed: Oct. 2, 1973 Print c ontrol logic circuitry for use in high speedon-the-fly impact printers, wherein at least one, but [21] Appl 402864preferably a plurality of independent, but interconnected dataprocessing circuit modules, each including [52] US. Cl.. l/93. 1fl 30/1l2,5 a separate free-running memorywith logic controlled [51] Int. ClB41j 7/08 dual line storage areas, effects sequential character [58]Field of Search 101/93 C; 340/1725 printing in a given line as the printdata is being reeeived, and simultaneous therewith allows for the tem-[56] References Cited porary storage of print data for the next adjacentline, UNITED STATES PATENTS when required. Through the utilization ofmodular 2,993,437 7/1961 Demer et al. 101 93 0 90115990901}, each911101111 d l may advantageously 3,289,576 12/1966 Bloom et al 101/93 cbe of ldemlcal qeslgm and m q Sltlgle lnte- 3,430,210 2/1969 Foure ct101/93 C X grated circuit ch1p, preferably usmg mexpenswe MOS- 3,463,0818/1969 Levine l 101/93 C FETS exhibiting relatively slow switchingspeeds, with 3,633,496 1/1972 Kearns 101/930 no sacrifice in printerperformance. 3,728,688 4/1973 Elmhurst et al 101/93 C X 3,732,408 5/1973Bettin 101 93 c x Claims, 15 Drawing Figures PROCESS CKTS MAX +0 w 11-CHAR y H BITS $20311 L\ 1 1 EMPTY I76 /74 :72039 v H INITIALIZE RNc W2SERIAL DATA 28119 H TcA sYNcl ll lo 11 LAST CKT I63 LAST v V H i 5 Li1L;l L 1 .L 9 L 1! I350 I F1RsT PROCESS CKT '1 1 I 1 LAST RRocEss CKT H u3440 *1 [TYRE cARR1ER oATA 1 ,NPUT TCR1SYNC) LOGIC FOR 20/" LOGlC FOR "7H I65 I 12 COLS 1 6 H H L11 OUTPU 1970 I J 3449 1 PRTHOTER t CONTROLLERPREV CKT PREV CKT 1 -f I FULL STATUS 1 FULL S ATUS 11 ,E OWN CKT I EOLOWN CKT i H 1|UNE FEED FULL sTATUs LINE FEED FULL STATUS 1 I69 MAGNETOR1vERs L 1| 1 3/59 F 1| 11 L H 831 INTERFACE 1 20 TO N \PARALLEL L12/PR1NT v INTERFACE MAGNETS 1 ONE PER COLUMN H PATENTEUNM 51974 3845710SHEET 01 [IF 12 HAMMER LOGIC TYPE CHAR. ADV PULSES PRINT CONTROL LOGICCIRCUITRY FOR ON-TI-IE-FLY PRINTERS BACKGROUND OF THE INVENTION 1. Fieldof the lnvention The present invention relates to printer apparatus and,more particularly, to logic control circuitry for selectively andsequentially controlling the line printing of type characters on-the-flyin such apparatus utilizing a continuously moving, endless type carrier.

2. Description of the Prior Art So-called on-the-fly printers, withwhich the present invention is primarily concerned, are of two basicimpact types. One type utilizes a rotating type character drum, and theother more recent, and generally preferred type, utilizes an endlesstype character chain or belt such as is described in Huntoon-Kearney US.Pat. No. 3,742,848, herein incorporated by reference.

ln all of these versions, the type supporting member is constructed andpositioned so as to carry one or more fonts of type characters past anarray of printinducing members, such as hammers, which are selectivelyactuated under the control of logic circuitry at.

the proper times, so as to effect the printing of the desired charactersat the proper positions alongsuccessive print lines of an indexableimprint character receiving medium, such as paper in either roll orsheet stock form.

One significant advantage of the belt or chain type printer over thedrum printer is that the two former versions do not present troublesomeproblems with respect to vertical registration of the printed characters(i.e., accurate alignment of the printed characters with respect to ahorizontal reference line). In drum printers vertical registration iscritically dependent on the timing of hammer actuation as the characterspass vertically thereby. This problem is essentially obviated in anendless carrier printer because both the carrier and the array ofhammers are juxtaposed in accurate parallel,

horizontal relationship across the width dimension of the paper.

Endless carriers also normally have the type characters mounted thereonin such a way that they are readily replaceable individually or as anentire font. In addition, both multiple identical and dissimilar fonts,having the same or different font lengths, mayalso be employed inendless carrier impact printers. This greatly increases the versatilityof the printer for specialized printing applications. Such characterfont versatility is not possible in drum printers because thecircumferentially disposed font of characters in every row must beidentical.

ln addition, as an endless type carrier allows the utilization of awider spacing between type characters than between hammers, referred toherein as a pitch relationship therebetween, the so-called problem ofghosting may be readily eliminated. Such a type characterhammerrelationship is described in the com monly assigned copendingapplication of Egon S. Babler, Ser. No. 268,236, now US. Patent3,795,187, herein incorporated by reference. Ghosting- (or shadowprinting) is a phenomenon which occurs as a result of a print hammer, inpressing the paper against the type character to be printed, alsocreating sufficient pressure to produce a slight impression on the paperof the edge of a type character adjacent to the character being printed.Such ghosting or shadow effects are particularly troublesome in drumprinters because the lateral spacing of the type characters in adjacentrows on the drum must necessarily be equal to the relatively closespacing of the associated print hammers.

Accordingly, while chain or belt type printers afford a number ofsignificant advantages over the drum printer, this does not mean thatthere are no serious problems involved in obtaining precise control overtype character-hammer registry while the former is moving on-the-fly.Such registry is very important, of course, if printed characterimpressions areto be not only uniformly spaced, but to exhibit distinct,sharp character line formations as required for esthetically pleasingand easily read copy.

Compounding the timing problems involved in endless type carrierprinters is the fact that with the spacing between adjacent typecharacters normally being purposely chosen to be greater than thespacing that exists between adjacent hammers, it becomes readilyapparent that at any given point in time during a print cycle, only afractional number of the hammers will simultaneously be in exactregistry with an equal number of type characters; preferably every thirdhammer as described in the above-cited Babler application. As such,

the hammer logic control circuitry must be capable of temporarilystoring the incoming data to be printed on a given line in a manner thatwill allow the sequential read out and utilization of that informationonly as the proper type characters on the carrier are brought intoalignment with the proper hammers (aligned with the print columns) foreach line to be printed.

Thus, the logic control circuit must be capable of serially receivingencoded input data to be printed, but thereafter printing that data in asequential rather than serial manner. Temporary memory storage of theinput data is necessary, of course, in order that every hammer, at somepoint in time during the printing of each line, be aligned with andcapable of effecting the printing of a character corresponding to everytype characters of a given font (or fonts) passing thereby.

suaiia time-delayed,sequential mode of hammer ac tuation, and the needtherefor, will be considered with respect to one particular belt printerof the type embodied herein wherein adjacent type characters on thecarrier having a spacing of 1.5 times the spacing between adjacenthammers as in the aforementioned Babler application. As such, everysecond type character may be brought into registry with every thirdprint hammer (and column) of an array thereof at any one time. Inasmuchas the type characters are moving at a constant rate of speed past thearray of hammers, it is readily seen that there are continuouslychanging groups of type characters and print hammers brought intoalignment during each print cycle. Thus, it can be readily seen thatwhen there are a large number of characters to be printed along a givenline, each print cycle may involve the printing of from 1 to the maximumnumber of type characters and hammers that can be aligned at any onetime during a print cycle. It thus follows that the characters andhammers involved in one print cycle normally would have no particularrelationship with the type characters and hammers involved in any otherof the print cycles required to complete the printing of a given line.

As described herein, the logic process of successively identifying eachgroup of characters that is sequentially brought into alignment with anassociated group of hammers is referred to as a sub-scan, with threesubscans constituting a scan period. A scan period is required toadvance the type carrier by a distance equal to the spacing between twoadjacent type characters. With the spacing between hammers (or columns)being equal to only two-thirds the spacing between type characters (fora l.5 pitch relationship therebetween), it is seen that in order toprint any given character of a font in any one of the column positionsof the printer, the number of sub-scans must equal 3 X N, where N is thenumber of character in the font.

It also logically follows that the shortest possible subscan printperiod for any new type character-column (hammer) alignment mustnecessarily encompass the time required for the carrier to be displacedone half the distance between hammers (or one-third the distance betweentype characters). ln one illustrative embodiment, this displacement ofthe type carrier requires 840 microseconds.

The logic control circuitry employed to effect highspeed impact printingon-the-fly" heretorfore has generally comprised a single storage memoryhaving a plurality of storage locations corresponding in number to thetotal number of print columns of the printer. Associated with the memorytypically are means for identifying the characters in the sequence inwhich they appear on the type carrier, means for actuating the hammersas the proper characters sequentially register therewith, means fortiming the various control and print functions, and means for initiatingand terminating the various electrical and mechanical operationsinvolved in connection with the operation of the printer.

With respect to the storage memory, it has generally comprised amagnetic core arranged in a particular core plane matrix having, forexample, a core plane for each bit of a chosen binary code, with eachplane comprising plural cores arranged in a row and columnconfiguration. Such a core plane matrix, for example, might comprise 160cores arranged in 16 rows of cores each so as to accommodate acorresponding number of print hammers.

Disadvantageously, such core memories require rather complex andexpensive (from a fabrication standpoint) X-Y read-write drivercircuitry, including X-Y windings, drivers, rings and switches. Suchmagnetic core matrices also often impose undesirable speed-powerrestrictions on the associated circuitry, as well as limitations on thesize and layout of the composite control circuitry.

More recently, advancements in solid state technology have resulted invery versatile and multi-faceted integrated circuitry referred to asmedium or large s ca 1e irTte g ration MSl or LSl). Particularly inapfiications where very high switching speeds have not been required,the active devices in such circuitry have increasingly been of themetal-oxide-semiconductorfield-effect type, hereinafter generallyreferred to as MOSFETs. Such devices have proven to be very effective,reliable, and readily amenable to high volume, low cost manufacture,even in rather complex, high density MSl or LSl circuitry. To that end,MOSFETs are gaining wide acceptance for use in the fabrication ofdiverse logic circuitry, including gates, inverters, flipflops,counters, shift registers, and the like.

With respect to printer logic control circuitry, however, all of therequired circuit logic cannot at present, at least, be economicallyfabricated on a single semiconductor chip. This has thus necessitated anumber of different logic circuit chips heretofore, with rather complexand extensive interfacing being required therebetween in order toassemble a composite printer hammer logic control circuit. This, ofcourse, does not lead to low cost, high yield composite circuits thatwould be possible if every circuit chip could be of identicalconstruction, be capable of independently processing print data for onlyan assigned subgroup of print columns, and be interconnected in asimple, modular fashion so as to constitute the complete logic circuitryfor an 80 column printer, for example.

Such a modular form of circuit construction would also have theadvantage that it would be conducive to accommodating printers with asmaller or larger number of print columns, typically ranging from to 132columns, for example, by simply adding or subtracting one or moreidentical circuit modules from the composite logic circuitry.Unfortunately, with most hammer logic control circuits employedheretofore, the maximum number of print columns that can normally becontrolled is fixed by unalterable circuit parameters.

Accordingly, there exists a definite need for a modular constructedhammer logic control circuit, particularly wherein the number of printcolumns chosen forany given application need not be divisable by anygiven number of identical circuit modules, each of which may be designednormally to accommodate and control the processing of print data for agiven predetermined number of print columns. To that end, what is neededis circuit modules designed to be compatible with simple, switch-optioncircuitry that may be employed outside of the last of a series ofmodular circuit chips, for example, so as to accommodate and control theprocessing of print data for any number of print columns less than thepredetermined number. In that way the need for any expensive, speciallydesigned circuit chips would be obviated.

A concomitant problem affecting both circuit speed requirements andtotal line printing speed in endless carrier, on-the-fly printersheretofore is related to the need to first store a complete line of databefore printing commences. This has generally been true whethersynchronous or asynchronous storage memories were employed, and whetherthe hammer-type character spacings were U16 same or different.

It is thus seen that there is a need for hammer logic control circuitryfor on-the-fly belt printers that can fully exploit the many advantagesof MOSFET circuitry, without requiring a cost-performance trade-off inthe logic circuitry in order to attain the high speed printing ratesdesired.

5 SUMMARY OF THE INVENTION It, therefore, is an object of the presentinvention to provide new and improved type character selection and printlogic control circuitry for use in on-the-fly high speed printerapparatus.

It is a further object of the present invention to utilize the virtuesof MOSFET integrated circuitry in on-the fly printer apparatus in amanner that allows reliable, simplified, low cost fabrication thereof,through the use of selective, logic controlled, dual line characterstorage read out of the information to be printed.

In accordance with the principles of the present invention, these andother objects are accomplished through the utilization of a plurality ofintercoupled, but independently operated data processing circuitmodules. Each module includes a free-running, logic controlled dual linestorage memory capable of selectively directing intput encoded characterdata into and out of either of two discrete storage areas thereof. Bothareas are associated with a specific and common subgroup of hammerslandprint columns), but each storage area is associated with a differentprint line. Such dual line storage'areas in each memory advantageouslyallows incoming data, often received at varying rates, to be temporarilystored for subsequent printing without having to resort to a batchprocess technique requiring an auxiliary main storage memory, forexample.

The utilization of multiple data processing circuit modules, with eachassociated with a different sub group of print hammers (and columns),advantageously allows the switching speeds of the various activeintegrated circuit elements embodied in each processing circuit to belower, for a given line printing speed, than would be possible with asingle-storage memory having sufficient storage for all of the characterdata to be printed along a given line. Considered more specifically,with each circuit module controlling only a fractional number of thetotal print hammers employed in a given printer, the number of storagepositions in the memory thereof are likewise reduced. Accordingly, thescanning .(or read out) rate of the circuit can be reduced, as thelimited number of encoded characters stored may be processed and printedindependently of, but concurrently with the input data received in andprocessed by the other circuit modules.

In contrast, with a typical single shift register type of memoryemployed heretofore, if there are 80 columns of possible data to bestored for subsequent printing along a given line, for example, thenthat data must normally be shifted through 80 elements of the shiftregister memory every time a different type character is brought intoalignment with a different column and associated hammer, until allpossible alignment combinations therebetween have been compared. It thusbecomes readily apparent that as the number of storage positionsrequired in the memory increase, the circuit logic switching speed ofnot only the memory, but of the other associated processing circuitrymust also increase for a given line printing speed.

The modular nature of the logic circuitry also has the advantage thatvarious length print lines can easily be accommodated by simply addingor subtracting one or more of the identical data processing circuit nodules as required for a given application. Moreover, in accordance withthe principles of the present invention, the number of print columnschosen need not be divisable by the standard number of columns assignedto each circuit module by design. Rather, each circuit module isdesigned so as to be compatible with outside strapoption circuitry so asto accommodate less than the standard number of print columns. Thus,there is no need for the last circuit module of a series, for example,to be specially designed to accommodate a nonstandard number of printcolumns.

As all of the circuit modules may be formed on discrete chips ofidentical integrated circuit design, chip size may be chosen to minimizecosts of both manufacture and composite circuit assembly, whilesimultaneously maximizing circuit chip yield and performance.

It is thus seen that the sub-divided, modular construction of the hammerlogic control circuitry embodied herein advantageously allows individualdata processing functions to be performed at a slower rate, for a givenline printing speed. This, in turn, makes it possible to exploit thedesired features and characteristics of inexpensively designed MOSFETintegrated circuitry, for example, without any adverse effect on printerperformance. Stated another way, the present modular logic circuitrydoes not necessitate the use of bi-polar active devices, or customizedMOSFET devices, fabricated through special and expensive processingtechniques, in order to achieve-the switching speed characteristicsotherwise required in prior hammer logic control circuits for a givenline printing rate.

The hammer logic control circuitry embodied in the present invention, aswill be discussed in greater detail hereinbelow, also exhibits a numberof other features and advantages relating not only to control of theprinter mechanism per se, but to the control of other importantoperating functions, such as error character detection, conditionalprocessing time out, data overloads, even and odd parity checks, andtest mode operations. The control circuitry is also designed to receiveStandard Serial Interface (SSI) information, with the modular dataprocessing circuits packaged on circuit cards for ease of assembly andmaintenance. The outputs from the circuit cards also advantageouslydrive the hammer magnets directly, which simplifies the hammer actuationcircuits and the wiring thereof.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partially broken awayperspective view of a high-speed impact printer, with some parts beingomitted for the purpose of illustration, together with a simplifiedblock diagram of the associated hammer logic control circuitry for usetherewith, which embodies features in accordance with the principles ofthe present invention;

FIG. 2 is a simplified schematic circuit diagram generally depicting themodular nature of the composite hammer logic control circuitry;

FIG. 3 is a simplified block diagram of the major associated circuitsembodied in one data processing circuit module of the composite hammerlogic control circuitry;

FIGS. 4A and 4B, in block diagram form, illustrate in greater detail thenature and functions of and the interconnected relationship between, allof the major circuits embodied in one processing circuit module;

FIG. is a more detailed block and schematic circuit diagram primarily ofthe logic controlled dual storage memory embodied in each of the dataprocessing circuit modules in accordance with the principles of thepresent invention;

FIG. 6 is a block and schematic circuit diagram illustrating in greaterdetail the association of the character position and print columncounters with respect to the load control circuitry disclosed onlygenerally in block diagram form in FIG. 4B;

FIG. 7 is a more detailed block and schematic circuit diagram primarilyof the character generating portion of one of the circuit modules of thecomposite logic control circuitry;

FIG. 8 is a block diagram of the hammer driver circuitry, includingclock and reset inputs associated therewith;

FIGS. 9 and 10 are detailed schematic circuit diagrams of interrelatedlogic circuitry for controlling the selective storage and read out ofdata from the dual storage areas of one of the circuit module memories,and for effecting the erasing of erroneous data from the memory,respectively;

FIG. 11 is a symbolic representation of two typical sub-scan alignmentpatterns at one point in time between certain print columns and typecharacters, having a 1.5 pitch relationship therebetween, for the firstand last of seven interconnected sub circuit processing modules;

FIG. 12 is a timing chart depicting the time duration and sequence ofthree sub-scans, for each of three successive print periods, relative tothe time delayed hammer firings initiated in response to each associatedsubscan;

FIG. 13 is a symbolic representation of the functional relationships,time-wise, between the slot positions in the position and columncounters relative to the slot positions in the dual storage areas of onefree-running storage memory; and

FIG. 14 is a timing chart illustrating certain printer control and dataprocessing control signals generated during a single line printingcycle.

DETAILED DESCRIPTION OF THE INVENTION GENERAL DESCRIPTION OF LOGICCONTROLLED PRINTER APPARATUS The logic control circuitry embodied hereinis particularly adapted for use in high speed, on-the-fly, impactprinters of the type depicted in FIG. 1. As disclosed therein, theprinter, identified'generally by the reference numeral 15, is of theclass that utilizes an endless type carrier 16, entrained about a pairof spaced and aligned sprockets or pulleys 17a and 17b, as described inthe aforementioned Huntoon-Kearney patent. The pulleys are journalled byany suitable means on the frame (not shown) of the impact printer. Thecarrier 16, which may comprise a chain or a toothed timing belt, isadapted to transport a plurality of type pallets 18 (only several shownin FIG. 1) in an essentially orbital path, which is oriented so as todefine upper and lower line printing courses in the areas generallydefined by the numerals 22 and 23, respectively.

Each-of the type pallets 18 has a front face portion havinga typecharacter die (not shown) secured thereto or otherwise formed as anintegral part thereof.

The pallets 18 are mounted on the carrier 16 and uniformly spaced andoriented transversely therealong by means of integral shank portions 18athat extend through suitably formed channels (not shown) formed in thecarrier. As will presently be seen, in accordance with the presentprinter embodiment, there are normally at least twice as many typepallets-characters on the carrier than in any chosen font. This meansthat a given sequence of characters is repeated more than once along theentire length of the carrier. If desired, of course, several fonts ofdifferent lengths could also be employed for a special printingapplication. For further details as to one preferred embodiment of thecarrier l6 and type pallets 18, including the mounting and drivingstructure associated therewith, reference is made to the aforementionedI-luntoon-Kearney patent.

In the illustrative embodiment of the printer depicted in FIG. 1,carrier pulleys 17a and 17b constitute idler and drive pulleysrespectively. Driving torque is contin- PQQSIYJEJLS LQQJ he p y J2.targgshashaft 24 which is coupled to a primeTnH er, hereinshown as amotor 26, through a drive train designated generally by a referencenumeral 27 in FIG. 1. The drive train includes a worm gear 28, securedto a shaft 30 of the motor 26, a gear 34, operably enmeshed with wormgear 28, and secured to one end of an elongated drive shaft 35, a wormgear 36, secured to the other end of the drive shaft 35, and a gear 38,operably enmeshed with worm gear 36. Gear 38 is secured to the same a zaasth BPIIQYWL a clutch 58, which may be of conventional design, ismounted in juxtaposition with gear 38 so as to releaseably couple asplit shaft 60 to the coextensively aligned shaft 24. Selectiveactuation of the clutch 58 iseffected through control signals generatedby the logic control circuitry embodied herein, as will be discussed ingreater detail hereinafter. Whenever the clutch 58 is operated it alsosupplies torque through a drive train not shown to incrementally advancea web 41, or paper on which printing is to take place in the directionshown by arrow 42, one line at a time.

For further details as to the drive trains for both the type carrier 16and the web 41, reference is again made to the I-Iuntoon-Kearney patent.

In the illustrative impact printer embodiment depicted in FIG. 1, thecharacter printing mechanism further comprises both an array ofspoke-like impellers 84 (only several shown in FIG. l), and a pluralityof respectively associated impactors, or print hammers, designatedgenerally by the reference numeral 85 (only several shown). There is oneimpeller and associated hammer for each possible printing position orcolumn across the width of the web 41, with the spaced impellers beingconcentrically secured to the longitudinally extending drive shaft 35.Each impeller 84 has a plurality of radially extending, uniformly spacedspoke-like impeller teeth or elements 84a, all of which are oriented ina common plane perpendicular to the axis of the shaft 35. In a preferredembodiment of the printer, the impellers 84 are preferably arranged in amanner as disclosed in the aforementioned copending Babler application.

Each hammer 85 is mounted in a channel (not shown) forming part of theprinter frame so as to be selectively driven along a rectilinear path,perpendicular to the web 41, between a normal, untensioned, ornonprinting position, and a printing position whereat an enlargedforward head portion 85a of each hammer is propelled against the backside of the web 22, as described in a second copending application ofEgon S. Babler, Ser. No. 268,237, filed July 3, 1972. In order tofacilitate printing at any given time, it is apparent that selectivehammers must be axially aligned respectively with different type pallets18, the latter being mounted in an array on the carrier 16, as describedhereinabove. As such, the continuous movement of the pallet-typecharacter assemblies along a path extending across the width of, andclosely adjacent to, the front side of the web 41, makes it possible foreach pallet 18 (with a type character die'on the front face thereof), orgroups thereof, tobe successfully brought into momentary axial alignmentwith the hammers 85.

The agency through which each impeller 84 drives an impeller 84 andhammer 85. The interponents 92 are disposed in a lateral array,extending parallel to and respectively aligned with the adjacent freerearward ends 8512 of the hammers 85. Briefly described herein, eachinterponent can be positioned in: (l) a first or vertically raised upperposition, with its upper free end portion disposed in the path ofmovement of a then immediately adjacent impeller spokelike element 84a(for transmitting force from the aligned impeller 84 to an alignedhammer 85), in consequence of which printing occurs; or (2) a second orvertically lowered, nonprinting position, in which the upper free endportion of the interponent 92 is displaced from the path of an impellerspoke 84a.

The manner in which the hammers 85 are mechani'- cally driven (asdistinguished from electronically controlled) against the web 41 formsno part of the present invention. For details relating to thecooperating mechanical relationship between the impellers 84, hammers 85and interponents 92, reference is made to the three copending Bablerapplications previously cited.

An inked ribbon 95, as depicted in only fragmentary form in FIG. 1, iscontinuously driven in one direction or the other between, and inalignment with, the array of type pallets 18 and the web 41. Onepreferred embodiment of an improved ribbon spool driving, reversing andtensioning mechanism for use with a printer of the type depicted in FIG.1 is disclosed in a copending application of A. F. Riley, Ser. No.345,407, filed Mar.

. 27, 1973, also assigned to the assignee of the present LII printer 15,as thus ,far described, constitutes a line- I at-a-time printer, i.e., aplurality of characters are normally sequentially printed across thewidth dimension of the web 41 during each of a plurality of print cyclesthat occur between successive index advancements of the web 41. Theprinting of actual images on the back or rear side of the 'web 41, as

-xie rqstiaELQj..lsisase mp shsst 9 searseby the impellers 84generating, and. transferring through the respectively associated andselectively actuated interponents 92, sufficient force: against therespectively associated hammers 85 to cause the latter to be drivenagainst the back side: of the web 41. The discrete hammer-propelledareas of the web 41 are then, in turn, driven against correspondinglyaligned areas of the aligned inked ribbon 95, and then driven againstthe particular type characters on the pallets 18 aligned therewith withsufficient force to effect controlled impact printing of characterimages on the front side of the web 11.

The logic control circuitry required to selectively and sequentiallyactuate the interponent-hammer combina tions through the energization ofrespectively associated electromagnets 126 will now be described ingreater detail. Mechanically, each electromagnet 126, when energized,serves to pivot a corresponding armature 127 such that it elevates aselected interponent 92 into the path of an oncoming impeller tooth 84a.This propels the associated] hammer against the backside of the web 41and thereby effects the printing of a character. The arrnatures 127 arepreferably arranged in accordance with a fourth copending Bablerapplication, Serial No. 292,003,

filed September 18, 1972, now issued as US. Patent 3,805,695, hereinincorporated. by reference. The electromagnets are also preferablyconstructed, arranged, and energized through physical circuitconnections in the manner described in the commonly assigned copendingapplication of James F. Kearney, Ser. No. 290,192, filed-Sept. 18, 1972,now U.S. Patent 3,785,283, and herein incorporated by reference.

As simply represented in block diagram form. in FIG. 1, a unique andimproved composite hammer logic control circuit, identified generally bythe reference numeral 130, is employed for sequentially energizing thehammer associated electromagnets 126 at the proper times, with respectto desired type character registration, in order to effect the printingof stored characters along each successive print line sequentially, butultimately positioned in the serial order in which they were initiallyreceived. It is to be understood, of course, that the hammer logiccontrol circuitry 130 described and claimed herein produces typecharacter-associated control signals, relative to selected columnpositions, that may be employed to actuate any type of print-inducingmeans, whether of the solenoid or magnet-driven hammer type, or of thenonhammer type, wherein selectively pulsed magnetic fields, for example,are utilized to inductively impact magnetic type characters mounted on anonmagnetic carrier, or disk, against a print medium.

CARRIER CONTROLLED TIMING CIRCUIT FOR COMPOSITE LOGIC CIRCUITRYtransducer 132, shown only symbolically, the basic timing signals,designated herein as a TYPE CARRIER ADVANCE (TCA) and a TYPE CARRIER AD-VANCE THREE (TCA-3) are generated to synchronize movement of the typecarrier 16 relative to the firing times of selected ones of the array ofhammers 85.

. Precise synchronization is very important, of course, if

accurate type character-hammer registration is to be established asrequired for high quality printing.

Each TCA pulse senses when a new type carrier-print column alignment hasoccured, and conditions the logic circuitry to start a new processcycle. Three TCA pulses occur while the type carrier moves the distancebetween two adjacent type pallets 18 (0.150 inch in one embodiment).Stated another way, a single TCA pulse occurs each time a type pallethas moved a third of the distance between adjacent type pallets, whichcorresponds to each possible printing instant as described in the Bablerapplication Ser. No. 268,236.

Each type carrier generated TCA pulse is thus employed to provide anindication to the hammer logic circuitry 130 (FIG. 1) that there is anew alignment of font. type characters and print columns of the printer.Each TCA-3 pulse is normally generated during every third TCA pulse timeslot and when it is missing from its customary third slot position, thisprovides an indication to the logic circuit that the first typecharacter of a given font on the carrier is aligned with the first, orsome other chosen print column position of the printer. A TYPE CHAR-ACTER RESET (TCR) pulse is then generated and indicates that the firsttype character of a font on the carrier 16 (represented by a 0, forexample), aligns with the first (or some other reference) col-- umnposition of the printer.

GENERAL DESCRIPTION OF l/O CONTROLLER AND OF LOGIC CONTROL CIRCUITRYWith particular reference now to FIG. 2, it is seen that an I/Ocontroller 134 essentially functions as a buffer between a conventionalStandard Serial Interface (SSI) and the composite hammer logic controlcircuit,

which actually comprises a plurality of essentially identical anduniquely interconnected data processing circuit modules 135. Inconjunction with one illustrative 80 column printer, the logic controlcircuitry, in accordance with one illustrative embodiment, employs sevenof such circuit modules 135 (only the first 135a andlast 135g beingshown in FIG. 2), with each of the first six performing the necessarylogic and data processing functions to effect the desired printing alongtwelve respectively associated columns of an eighty column printer.This, of course, results in the seventh subcircuit module 135g beingassociated with only the last eight columns constituting a print line.It is to be understood that each circuit module 135 can be readilyconstructed to process the necessary print data and control the firingof either a larger or a smaller number of print hammers, and that thereis no limit on the number of circuit modules that may be utilized in theinterconnected manner depicted in FIG. 2.

As also seen in FIG. 2, each of the circuit modules 135 has a number ofcontrol leads connected to the input/output (I/O) controller 134,whichmay be of conventional design. The purpose of the controller is toreceive incoming encoded data to be printed, such as from theaforementioned conventional Standard Serial Interface (SSI), and totransform that data into the desired binary encoded form, including thenecessary control information to operate the printer mechanism.

Considered more specifically, the input data to be processed forprinting, when of a common format known as the American Standard Codefor Information Interchange (ASCII), for example, wherein the binarynumbers 1 throughj32 constitute special commands for non-printablecharacters, and the numbers 33 through 126 constituted printablecharacter data, is changed into a format of weighted binary order so asto be com patible with the logic circuitry embodied herein.

This data is received by and transmitted from the I/O controller 134, asdepicted in FIG. 2, over a four wire (double twisted pairs) input/outputconnection designated generally by the reference numeral 141, from aconventional parallel interface 142, which serves no part of the presentinvention and, thus, is shown only symbolically. The data transmittedover the two twisted pairs of leads 141 is accomplished, for example, byswitching the operating signal currents, between voltage levels of O and5 volts DC, supplied from a voltage source (not shown). A conventionaldifferential receiver (not shown) in the I/O controller 134, may be usedto detect the resulting voltage shifts.

In one preferred embodiment, all print data (i.e., ASCII print data andmessage control characters), as well as other necessary controlinformation for the printer, is sent to the logic control circuitry 130in the form of an 18-bit word, with such data being transmitted seriallyat 56 k baud. Only control information is sent from the printer to theI/O controller 134.

As depicted in FIG. 2, the most significant nonprintable commandsignals, identified by their respectively associated leads, comprise theTYPE CARRIER ADVANCE (TCA) sync lead 163, TYPE CARRIER RESET (TCR) synclead 165, END OF LINE (EOL) lead 168, LINE FEED lead 169, REQUEST NEXTCHARACTER (RNC) lead 172, INITIALIZE lead 174, and EMPTY lead 176. Aswill be described in greater detail in connection with FIG. 10, the EOLlead 168 actually includes what essentially constitutes a common OR-busson which EOL signals may be sent from the [/0 controller 134 or fromcircuit module 135g to all other circuit modules 135, under specifiedcircumstances. Similarly, the LINE FEED lead 169 also includes whatessentially constitutes an AND-buss, in that all of the circuit modulesmust send a LINE FEED signal (l) to the I/O controller before thelatter, after a specified time duration, forces the bus to a NO LINEFEED state (0). The circuit modules 135 then detect this latter stateand release the LINE FEED lead 169. The significance of all of thecontrol signals will be described in greater detail hereinafter.

The printable character data, as distinguished from the non-printablecommand signals, is transmitted over Serial Data lead 181, and generallycomprises encoded alphanumeric characters, punctuation marks, etc.

As is also readily seen in FIG. 2, all of the inputoutput leads of thecontroller 134, with the exception of the TCR lead 165, are directlyconnected to each of the logic circuit modules 135a-g. The TCR signal issuccessively passed from one sub-circuit module 135 to the next aftersome internal logic functions are carried out. Considered only brieflyat this point, before each circuit module 135 is ready to process printdata and to selectively actuate any of the proper hammers 85 associatedtherewith, after it has been INITIALIZED, it must have received a TCRsignal and passed it through its own circuit module to the next one.

A given circuit module 135 accepts coded input data to be printed onlyif the immediately preceding circuit module has the proper 12 columnstorage area full, and if its own proper 12 column memory storage areais not full. This, of course, does not mean that there has to be aprinting character stored in every slot position of a merals 205a and205g in FIG. 2.

given storage area, as there may be one or more columns where no data isto be printed (as represented by SPACE characters), or where a characterhas already been printed and the memory slot therefore is empty. In suchcases, the circuitry simply recognizes this fact and acts as if thememory were full.

A PREV CKT FULL STATUS signal is shown only symbolically in FIG. 2 byleads 197a and g within the outline of the first and seventh circuitmodules 135a and g. The OWN CKT FULL STATUS signal is similarly onlyshown symbolically by leads 199a and g in the same circuit modules. Thelogic circuits for these signals and their significance will bedescribed in greater detail in connection with a description of thecomposite hammer logic circuitry depicted in FIGS. 3-10.

A signal lead 201 connects each successive circuit module to the next,and actually comprises an extension of the TCR lead 165 depicted in FIG.2. As the lead 201 actually interconnects successive modules 135, it isshown symbolically in FIG. 2 as having both an output portion 201" andan input portion 201'. In actual operation, two different encodedsignals are multiplexed on the intercoupling lead 201, one signalcomprises OWN CKT FULL STATUS information with respect to a particularpreceding adjacent one of the circuit modules 135b-g (excluding 135a andthe other signal comprises TYPE CARRIER RESET (TCR) information. TheTYPE CARRIER RESET (TCR) information is shifted into and out of each ofthe seven circuit modules 135a-g in succession.

Considered more specifically, the TCR signal trans- 'mitted over thelead 201 is actually shifted through an eight element shift register 261(not shown in FIG. 2, but described below in connection with FIGS. 3 and4), at a rate corresponding to the periodic alignment of type characterswith print column positions (or hammers) of the printer. As mentionedhereinabove, the generation of the LINE FEED (lead 169) and EOL (lead168) signals between the I/O controller and circuit modules controls theprocessingof each new line Y of binary encoded information, and theultimate printing of the characters represented thereby. 7

Two additional inputs to each circuit module 135, which are identifiedby leads 203a and 203g in FIG. 2,

' has a type pallet mounted therein. As a SPACE is not provideinformation as to the number of characters in the largest character fonton the type carrier. The significance of these inputs will become moreapparent hereinbelow. A

As also generally depicted in FIG. 2, each circuit module 135 produces amaximum of 12 possible output print signals for respectively drivingdirectly, and selectively, 12 hammers 85 (FIG. 1), or any other type ofprint-inducing means, out of the total array thereof, which total isequal to the number of print columns of the printer. These signals arerespectively sent over 12 output leads designated generally by thereference nu- A plurality of printersignal control leads, forming a partof a cable 210 in FIG. 2, also interconnect the I/O controller 134 withthe printer. Such printer control leads transmit the necessary controlsignals to effect, or provide information of, by way of example, thefollowing printer conditions: forms versus roll paper, single versusdouble line feed, low paper, paper out, local line feed versus formfeed, end of forms, line feed magnet energization, and motor on/off.These signals are normally not binary encoded and may be generated assimple voltage level changes in a conventional manner and, thus, willnot be considered in further detail herein. The previously mentioned TCAand TCA-3 signals, produced for carrier hammer synchronization, are alsotransmitted between the I/O controller 134 and the transducer 132,associated with the printer carrier 16, over separate leads in the groupforming the cable 210 in FIG. 2.

Before considering the basic logic circuitry in greater detail, it isbelieved beneficial to describe at this point the nature of the font(s)carried by the carrier 16, as well as the manner in which they arepositioned on the type pallets 18 in two illustrative impact printers.In an column printer, for example, the type carrier has 192 type palletsmounted within a corresponding number of slots spaced equidistanttherealong, whereas in i a printing character (although it is assigned atype pallet slot), the type pallet for a predetermined ERROR symbol isinserted in that slot. This. ERROR pallet also identifies the particularfont set, if two are employed, by means of two peculiar alphacharacters, for example, formed on the face of the type pallet inquestion.

When two or more fonts are employed, they may be of equal or differentlengths, with each being repeated as often as is required in order tocompletely fill the slots in the type carrier 16. As each of thecharacter fonts, as previously mentioned, must begin with a SPACE, allof the characters of the shorter font are necessarily contained in thelonger font. The 64 (including SPACE) and 96 (including SPACE and DE-LETE) character fonts are most commonly used, as three fonts of theformer and two of the latter will evenly fill the 192 pallet slots inthe carrier of an 80 column printer. To fit a 64 character font on thecarrier for a I32 column printer of the type embodied herein, fourcomplete, fonts plus the first 32 characters of a fifth font would berequired to fill the 288 slots in the carrier with pallet-characters.

OVERVIEW OF INDIVIDUAL CIRCUITS FORMING ONE COMPLETE CIRCUIT MODULEAttention is now directed to FIG. 3, which discloses in simplified formthe basic hammer logic circuitry as embodied in just one of theessentially identical data processing circuit modules l35a-g depictedonly symbolically in FIG. 2. A more detailed description of thecircuitry and of the various functions thereof will be described inconnection with a discussion of FIGS. 4-10 hereinbelow. A A

Starting at the point of data entry in FIG. 3, the print data initiallyis typically received in preferably converted ASCII data format from theoutput of the I/O controller 134 in serial format, and then suppliedthrough a shift register 220 to a dual storage freerunning memory 221.As previously mentioned, the memory is effectively sub-divided. into twodistinct l2

1. A print control logic circuit for use in high speed on-theflyprinters, for selectively actuating one or more out of a plurality ofcharacter print-inducing members whenever selective type charactersforming a part of a continuously moving font of type characters aremomentarily brought into respectively aligned and juxtaposedrelationship with said print-inducing members so as to effect sequentialprinting of type character images along each successive line on amedium, but with the character images ultimately being positioned in theserial order in which the input data characters to be printed werereceived, said logic control circuit comprising: sub-dividable memorymeans for storing input binary encoded data representative of thecharacters to be printed at particular positions along a given printline, said memory means having at least two logic controlled andoperationally distinct storage areas, and including means forselectively storing input character data in and reading said data out ofsaid storage areas in a manner that allows incoming data intended forprinting on one line to be stored in one of said distinct storage areaswhile any previously received data is still being read out of the otherstorage area, processed and printed in the preceding line, means forgenerating type character font data in multiple phase sequences duringeach print cycle, said data being representative of and identifying theparticular ones of said moving font type characters that arerespectively brought into registry with associated ones of saidcharacter print-inducing members at any particular point in time duringeach phase sequence, and means for processing any stored character datafor printing after having been read out of said memory means, bycomparing said stored data with said generated type character data, andfor generating a distinct print signal, in response to each valid equalsignal comparison, for use in actuating at the proper time theparticular one of an associated character print-inducing member thatwill effect the printing of a character image representative of thecompared type character at the proper position along a given print line.2. A print control logic circuit in accordance with claim 1 wherein saidmemory means includes a free-running memory, and phase controlled typecharacter position and print column counter means for logicallycontrolling access to and sub-dividing said memory into distinct dualstorage areas.
 3. A print control logic circuit in accordance with claim1 wherein said circuit is sub-divided into a plurality of essentiallyidentical, but interconnected data processing circuit modules, eachcircuit module including separate ones of said memory means, charactergenerating means and comparing means, and with each circuit module beingassigned to process print data for a pre-determined number of printcolumns forming only a sub-group out of the total number of printcolumns defining the length of a given print line, with each circuitmodule thereby storing, processing and effecting the printing of inputdata characters as received in only the print columns assigned thereto.4. A print control logic circuit in accordance with claim 2 wherein saidmemory means further includes memory recovery circuit means fordetecting the presence of and effecting both the erasing of any invaliddata characters stored in said memory during the printing of each printline, and the printing of error symbols therefore.
 5. A print controllogic circuit in accordance with claim 2 wherein said memory meansfurther includes: presettable strap-option circuit means coupled to saidassociated memory for detecting the presence of and purging said memoryof any invalid data characters stored therein whenever such charactersrepresent an encoded binary number higher than a preset numberrepresentative of the highest order character in a chosen font of typecharacters employed in a given application.
 6. A print control logiccircuit in accordance with claim 5 further comprising: an auxiliaryinvalid character recovery circuit associated with said memory means andbeing capable of detecting any invalid data characters stored in saidmemory means, and for optionally erasing said invalid charactersindependently of said strap-option circuit means, regardless of thelength of a given character font employed in conjunction therewith,after a predetermined time delay that is chosen to be greater than thetime required for the number of different type character fonts employedto successively pass a given reference point of the printer, and forthereafter causing each equal character-signal comparison representativeof an invalid data character to effect the actuation of the properprint-inducing member at the proper time when an error symbol characterincluded in a given font of type characters is momentarily brought intoregister therewith and, thereby, effect the printing of an error symbol.7. A print control logic circuit in accordance with claim 3 wherein saidmemory means of each of said circuit modules further includes means forselectively generating first and second storage signals and first andsecond processing signals for controlling the loading of encoded datacharacters in and the readout thereof from the first and second storageareas of said memory means in a selective manner.
 8. A print controllogic circuit in accordance with claim 7 wherein the generated storageand processing signals are associated with the same storage areas of thememory means unless input data characters are received for storage afterone storage area of said memory means has been filled, but theprocessing and printing of that data has not been completed.
 9. A printcontrol logic circuit in accordance with claim 3 wherein each of saidmemory means includes a free-running storage memory and phase-controlledtype character position and print column counter means for logicallycontrolling selective access to and sub-dividing said memory into dualstorage areas, and wherein each of said circuit modules furthercomprises: memory recovery circuit means for detecting the presence ofand effecting the erasing of any invalid data characters stored in saidassociated memory during the printing of each print line, and foreffecting the printing of error symbols therefor.
 10. A print controllogic circuit in accordance with claim 9 wherein each of said circuitmodules further comprises: circuit means for generating line stackingcontrol signals for over-riding the normal operation of said associatedmemory so as to allow character data received at a rate faster than theprinter can print the data stored in a first storage area of saidmemory, for a given line, to be temporarily stored in the second of saidstorage areas for not only the adjacent print line, but for anysucceeding line thereafter until said second storage area has beenfilled, subject to any data for any line after the adjacent line, havingnot been previously transferred to said first storage area in the normalmanner upon the processing and printing of the previously storedcharacter data therein having been completed.
 11. A print control logiccircuit in accordance with claim 9 wherein said memory recovery circuitmeans in each of said circuit modules comprises presettable strap-optioncircuit means coupled to said associated memory for detecting thepresence of and purging said memory of any invalid data charactersstored therein whenever such characters represent an encoded binarynumber higher than a preset number representative of the highest ordercharacter in a chosen font of type characters employed in a givenapplication.
 12. A print control logic circuit in accordance with claim11 wherein each of said circuit modules further comprises: an auxiliaryinvalid character recovery circuit capable of detecting any invalid datacharacters stored in said associated memory, and for erasing saidinvalid characters independently of said strap-option circuit means,regardless of the length of a given character font employed inconjunction therewith, after a predetermined time-delay that is chosento be greater than the time required for the number of different typecharacter fonts employed to successively pass a given reference point onthe printer, and for thereafter causing each equal character signalcomparision representative of an invalid data character to effect theactuation of the proper print-inducing member at the proper time when anerror symbol character included in a given font of type characters ismomentarily brought into register therewith, thereby effecting theprinting of an error symbol.
 13. A print control logic circuit inaccordance with claim 9 wherein each of said processing circuit modulesfurther includes: pulse-stretching means associated with the comparingand print signal generating means so as to allow said print signals tobe respectively and selectively generated for a longer time period thanis encompassed by the predetermined number of sub-scan periods defininga given print cycle.
 14. A print control logic circuit in accordancewith claim 9 wherein each of said processing circuit modules furtherincludes: means for genrating timing pulses in response to and dependenton the rate of speed at which each type character font moves past theprint columns, to operate the circuitry in each circuit module in amanner which maintains a continuous synchronous relationship between thefont type character signals generated and the read out of stored datacharacters from the associated memory during each sub-scan period, saidtiming pulses being transmitted in succession to the serially connectedcircuit modules.
 15. A print control logic circuit in accordance withclaim 14 wherein each of said circuit modules further includes: meansfor generating an own circuit full status signal whenever a givenstorage area of said memory has been filled with data characters to beprinted, and shift register means, responsive to said timing pulses, foreffecting the multiplexing of said timing pulses with said own fullstatus signals, and for transmitting said pulses and signals to the nextsucceeding circuit module, but in a manner contingent upon all of thedata characters to be stored, processed and printed by each precedingcircuit module having been received and, as a result thereof, havinggenerated its own circuit full status signal and then multiplexed thatsignal with a previously received timing pulse and transmitted both tothe next succeeding circuit module which similarly responds thereto, inserial fashion.
 16. A print control logic circuit in accordance withclaim 14 wherein each of said processing circuit modules furtherincludes: means responsive to externally controlled signal stimulus forallowing each circuit module to receive, store and process characterprint data for any selected number of assigned print columns less thanthe maximum number of print columns that may be assigned to each circuitmodule by circuit design.
 17. A print control logic circuit inaccordance with claim 12 wherein each oF said circuit modules furtherincludes: pulse-stretching means associated with the comparing and printsignal generating means so as to allow said print signals to berespectively and selectively generated for a longer time period than isencompassed by the predetermined number of sub-scan periods defining agiven print cycle, and means for generating timing pulses in response toand dependent on the rate of speed of each character font in moving pastthe print columns, to operate the circuitry in each circuit module in amanner that maintains a continuous synchronous relationship between thefont type character signals generated and the read out of stored datacharacters from the associated memory during each sub-scan period, saidtiming pulses being transmitted in succession to the serially connectedcircuit modules.
 18. A print control logic circuit in accordance withclaim 17 wherein each of said circuit modules further includes: meansfor generating an own circuit full status signal whenever a givenstorage area of said memory has been filled with data characters to beprinted, shift register means, responsive to said timing pulses, foreffecting the multiplexing of said timing pulses with said own fullstatus signals, and for transmitting said pulses and signals to the nextsucceeding circuit module, but in a manner contingent upon all of thedata characters to be stored, processed and printed by each precedingcircuit module having been received and, as a result thereof, havinggenerated its own circuit full status signal and then multiplexed thatsignal with a previously received timing pulse and transmitted both tothe next succeeding circuit module which similarly responds thereto, inserial fashion, and means responsive to external signal stimulus forallowing each circuit module to receive, store, and process characterprint data for any selected number of assigned print columns less thanthe maximum number of print columns that may be assigned to each circuitmodule by circuit design.
 19. A print control logic circuit for use inon-the-fly impact printers, for selectively actuating one or more out ofa plurality of character print-inducing members whenever selective typecharacters forming a part of a continuously moving font of typecharacters are momentarily brought into respectively aligned andjuxtaposed relationship with said print-inducing members so as to effectsequential printing of type character images along each successive lineon a medium, but with the character images ultimately being positionedin the serial order in which the input data characters to be printedwere received, said logic control circuit comprising: a plurality ofessentially identical, but interconnected data processing circuitmodules, each one being assigned to process print data for apre-determined number of print columns forming only a sub-group out ofthe total number of print columns defining the length of a given printline, with each circuit module thereby storing, processing and effectingthe printing of input data characters as received in only the printcolumns assigned thereto, each of said circuit modules including:sub-dividable memory means for storing input binary encoded datarepresentative of the characters to be printed at particular positionsalong a given print line, said memory means including a free-runningstorage memory having two logic controlled storage areas, and furtherincluding phase controlled logic circuit means for selectively storinginput character data in and reading said data out of said storage areasin a manner that allows incoming data intended for printing on one lineto be stored in one of said distinct storage areas while any previouslyreceived data is still being read out of the other storage area,processed and printed in the preceding line, said phase controlledcircuit means including a phase counter, a type character positioncounter and a print column counter to control the selective loading ofdata Characters in and their read out from the two storage areas of saidmemory, means for generating type character data in multiple phasesequences during each print cycle, said data being representative of andidentifying the particular ones of said moving font type characters thatare respectively brought into registry with associated ones of saidcharacter print-inducing members at any particular point in time duringeach phase sequence, and means for processing said stored data forprinting after it has eeen selectively read out of said storage areas ofsaid memory, by comparing it with said generated type character data,and for generating a distinct print signal, in response to each validequal signal comparison, for use in actuating at the proper time theparticular one of the associated character print-inducing members thatwill effect the printing of a character image representative of thecompared type character at the proper position along a given print line.20. A print control logic circuit in accordance with claim 18 whereineach of said circuit modules further includes: means for generatingtiming pulses in response to and dependent on the rate of speed at whicheach type character font moves past the print columns to operate thecircuitry in each circuit module in a manner that maintains a continuoussynchronous relationship between the font character signals generatedand the read out of stored data characters from the associated memoryduring each sub-scan period, said timing pulses being transmitted insuccession to the serially connected circuit modules, memory recoverycircuit means for detecting the presence of and effecting the erasing ofany invalid data characters stored in said associated memory during theprinting of each print line, and for effecting the printing of errorsymbols therefor, means for selectively generating first and secondstorage signals and first and second processing signals, for controllingthe loading of encoded data characters in and the read out thereof fromthe first and second storage areas of said memory in a selective manner,and pulse-stretching means associated with the comparing and printsignal generating means so as to allow said print signals to berespectively and selectively generated for a longer time period than isencompassed by the predetermined number of sub-scan periods defining agiven print cycle.
 21. A print control logic circuit in accordance withclaim 20 wherein each of said memory recovery circuit means comprisespresettable strap-option circuit means coupled to said associated memoryfor detecting the presence of and purging said memory of any invaliddata characters stored therein whenever such characters represent anencoded binary number higher than a preset number representative of thehighest order character in a chosen font of type characters employed ina given application, and wherein each of said circuit modules furthercomprises: circuit means for generating line stacking control signalsfor over-riding the normal operation of said associated memory so as toallow character data received at a rate faster than the printer canprint the data stored in a first storage area of said memory, for agiven print line, to be temporarily stored in the second of said storageareas for not only the adjacent print line, but for any succeeding linethereafter until said second storage area has been filled, subject toany data for any line after the adjacent line, having not beenpreviously transferred to said first storage area in the normal mannerupon the processing and printing of the previously stored character datatherein having been completed; an auxiliary invalid character recoverycircuit capable of detecting any invalid data characters stored in saidassociated memory, and for optionally erasing said invalid charactersindependently of said strap-option circuit means, regardless of thelength of a given character font employed in conjunction therewith,after A predetermined time-delay that is chosen to be greater than thetime required for the number of different type character fonts employedto successively pass a given reference point on th printer, and forthereafter causing each equal character signal comparison representativeof an invalid data character proper time when an error symbol characterincluded in a given font of type characters is momentarily brought intoregister therewith and, thereby, effect the printing of an error symbol,and strap-option circuit means for allowing each circuit module toreceive, store and process character print data for any selected numberof assigned print columns less than the maximum number of print columnsthat may be assigned to each circuit module by circuit design.
 22. In aprinter mechanism including a moving type carrier having at least onefont of characters positioned therealong, a plurality of actuableprint-inducing members aligned with the carrier, and an input-outputcontroller for interfacing the incoming encoded print data with theprinter, a print control logic circuit for use in generating characterprint signals to selectively actuate one or more of the print-inducingmembers out of a plurality of such members when selected ones thereofare periodically and sequentially momentarily aligned with selected andrespective ones of said type characters members in accordance with theorder in which input data characters are received by the control circuitfor subsequent printing, said circuit comprising: sub-divided memorymeans for storing input binary encoded data representative of thecharacters to be printed at particular positions along a given printline, said memory means having at least two logic controlled andoperationally distinct storage areas, and including means forselectively storing encoded character data in and for reading said dataout of said storage areas of said memory means in a manner that allowsincoming data intended for printing on one line to be stored in one ofsaid distinct storage areas, while any previously received data is stillbeing read out of the other storage area, processed and printed in thepreceding line, means for generating type character font data in apredetermined number of phase sequences during each print cycle, saiddata being representative of and identifying the particular ones of saidfont type characters on said continuously moving carrier that arerespectively brought into registry with associated ones of saidcharacter print-inducing members at any particular point in time, duringeach phase sequence, the number of said phase sequences being dependenton the relationship between the spacing of adjacent type characters onthe carrier and the spacing of print-inducing members, with the spacingof the former being wider and with the number of phase sequences beingchosen so as to allow every type character to be brought into alignmentwith every print-inducing member during a given print cycle, and meansfor processing any stored character data for printing after it has beenread out of said memory means, by comparing said stored data with saidgenerated type character data, and for generating a distinct printsignal, in response to each valid equal signal comparison, for use inactuating at the proper time the particular one of the characterprint-inducing members that will effect the printing of the desiredcharacter image representative of the compared type character at theproper position along a given print line in accordance with the order inwhich the input data characters were received for printing.
 23. In aprinter mechanism in accordance with claim 22, said print control logiccircuit being sub-divided into a plurality of essentially identical, butinterconnected data processing circuit modules, each circuit moduleincluding separate ones of said memory means, character generating meansand comparing means, and with each circuit module being assigned toprocess print data for a pre-determined nuMber of print columns formingonly a sub-group out of the total number of print columns defining thelength of a given print line, with each circuit module thereby storing,processing and effecting the printing of input data characters asreceived in only the print columns assigned thereto.
 24. In a printermechanism in accordance with claim 23, said memory means of each of saidcircuit modules including a free-running memory, phase controlled typecharacter position means and print column counter means for logicallycontrolling access to and sub-dividing said memory into distinct dualstorage areas, and memory recovery circuit means for detecting thepresence of and effecting the erasing of any invalid data charactersstored in said memory during the printing of each print line.
 25. In aprinter mechanism in accordance with claim 24, each of said recoverymeans of said control circuit further including: presettablestrap-option circuit means copuled to said associated memory fordetecting the presence of and purging said memory of any invalid datacharacters stored therein whenever such characters represent an encodedbinary number higher than a preset number representative of the highestorder character in a chosen font of type characters employed in theprinter mechanism, and for thereafter causing each equal charactersignal comparison representative of an invalid data character to effectthe actuation of the proper print-inducing member, corresponding inposition to the position in which the invalid data character is storedin the memory, at the proper time when an error symbol type characterincluded in a given font of type characters carried on the carrier ismomentarily brought into registry therewith, thereby effecting theprinting of an error symbol.
 26. In a printer mechanism in accordancewith claim 25, each of said processing circuit modules of said controlcircuit further including: an auxiliary invalid character recoverycircuit capable of detecting any invalid data characters stored in saidassociated memory, and for optionally erasing said invalid charactersindependently of said strap-option circuit means, regardless of thelength of a given character font employed in said printer mechanism,after a predetermined time-delay that is chosen to be greater than thetime required for the number of different type character fonts employedto successively pass a given reference point on the printer, and forthereafter causing each equal signal comparison representative of suchan invalid data character to effect the actuation of the properprint-inducing member, corresponding in position to the particularposition in which the invalid data character was initially stored insaid memory, at the proper time when an error symbol character includedin a given font of type characters carried on the carrier is momentarilybrought into register therewith, thereby effecting the printing of anerror symbol, and pulse-stretching means associated with the comparingand print signal generating means so as to allow said print signals tobe respectively and selectively generated for a longer time period thanis encompassed by the predetermined number of sub-scan periods defininga given print cycle.
 27. In a printer mechanism including a moving typecarrier having at least one font of type characters positionedtherealong, a plurality of actuable print-inducing members aligned withthe carrier, and an input-output controller for interfacing the incomingencoded print data with the printer mechanism, a print control logiccircuit for use in generating print signals to selectively actuate oneor more of the print-inducing members out of a plurality of such memberswhen selected ones thereof are periodically and sequentially momentarilyaligned with selected and respective ones of said type characters inaccordance with the order in which input data characters are received bythe control circuit for subsequent printing, said circuit comprising: aplurality oF essentially identical, but interconnected data processingcircuit modules, each one being assigned to process print data for apre-determined number of print columns forming only a sub-group out ofthe total number of print columns defining the length of a given printline, with each circuit module thereby storing, processing and effectingthe printing of input data characters as received in only the printcolumns assigned thereto, each of said circuit modules including:sub-dividable memory means for storing input binary encoded datarepresentative of the characters to be printed at particular positionsalong a given print line, said memory means including a free-runningstorage memory having two logic controlled storage areas, and furtherincluding phase controlled logic circuit means for selectively loadinginput character data in and reading said data out of said storage areasin a manner that allows incoming data intended for printing on one lineto be stored in one of said distinct storage areas while any previouslyreceived data is still being read out of the other storage area,processed and printed in the preceding line, said phase controlledcircuit means including a phase counter, a type character positioncounter and a print column counter to control the selective loading ofdata characters in and their read out from the two storage areas of saidmemory, means for generating type character data in multiple phasesequences during each print cycle, said data being representative of andidentifying the particular ones of said moving font type characters thatare respectively brought into registry with associated ones of saidcharacter print-inducing members at any particular point in time duringeach phase sequence, and means for processing any stored character datafor printing after it has been read out of said free-running memory, bycomparing said stored data with said generated type character data, andfor generating a distinct print signal in response to each valid signalcomparison, for use in actuating at the proper time the particular oneof the character print-inducing members that will effect the printing ofthe desired character image representative of the compared typecharacter at the proper position along a given print line.
 28. In aprinter mechanism in accordance with claim 27, each of said processingcircuit modules of said control circuit further including: means forgenerating timing pulses in response to and dependent on the rate ofspeed at which each type character font moves past the print columns, tooperate the circuitry in each circuit module in a manner that maintainsa continuous synchronous relationship between the font type charactersignals generated and the read out of stored data characters from theassociated memory during each sub-scan period, said timing pulses beingtransmitted in succession to the serially connected circuit modules,memory recovery circuit means coupled to said associated memory fordetecting the presence of and effecting both the erasing of any invaliddata characters stored in said memory during the printing of each printline, and the printing of error symbols therefor, and wherein each ofsaid memory means further includes: means for selectively generatingfirst and second storage signals and first and second processingsignals, for controlling the loading of encoded data characters in andthe read out thereof from the first and second storage areas of saidmemory in a selective manner.
 29. In a printer mechanism in accordancewith claim 28, each of said memory recovery circuit means furthercomprising presettable strap-option circuit means coupled to saidassociated memory for detecting the presence of and purging said memoryof any invalid data characters stored therein whenever such charactersrepresent an encoded binary number higher than a preset number ofrepresentative of the highest order character in a chosen font of typecharacters employed in a given application, anD wherein each of saidcircuit modules further comprises: pulse-stretching means associatedwith the comparing and print signal generating means so as to allow saidprint signals to be respectively and selectively generated for a longertime period than is encompassed by the predetermined number of sub-scanperiods defining a given print cycle.
 30. In a printer mechanism inaccordance with claim 29, each of said circuit modules furtherincluding: an auxiliary invalid character recovery circuit capable ofdetecting any invalid data characters stored in said associated memory,and for optionally erasing said invalid characters independently of saidstrap-option circuit means, regardless of the length of a givencharacter font employed in conjunction therewith, after a predeterminedtime-delay that is chosen to be greater than the time required for thenumber of different type character fonts employed to successively pass agiven reference point on the printer mechansim, and for thereaftercausing each equal character signal comparison representative of aninvalid data character to effect the actuation of the properprint-inducing member at the proper time when an error symbol characterincluded in a given font of type characters is momentarily brought intoregister therewith, thereby effecting the printing of an error symbol,and operable circuit means within each circuit module, responsive to anexternally applied signal, for allowing each circuit module to receive,store and process character print data for any selected number ofassigned print columns less than the maximum number of print columnsthat may be assigned to each circuit module by circuit design.